Application of Silicon Photomultipliers to Positron Emission Tomography

Historically, positron emission tomography (PET) systems have been based on scintillation crystals coupled to photomultipliers tubes (PMTs). However, the limited quantum efficiency, bulkiness, and relatively high cost per unit surface area of PMTs, along with the growth of new applications for PET, offers opportunities for other photodetectors. Among these, small-animal scanners, hybrid PET/MRI systems, and incorporation of time-of-flight information are of particular interest and require low-cost, compact, fast, and magnetic field compatible photodetectors. With high quantum efficiency and compact structure, avalanche photodiodes (APDs) overcome several of the drawbacks of PMTs, but this is offset by degraded signal-to-noise and timing properties. Silicon photomultipliers (SiPMs) offer an alternative solution, combining many of the advantages of PMTs and APDs. They have high gain, excellent timing properties and are insensitive to magnetic fields. At the present time, SiPM technology is rapidly developing and therefore an investigation into optimal design and operating conditions is underway together with detailed characterization of SiPM-based PET detectors. Published data are extremely promising and show good energy and timing resolution, as well as the ability to decode small scintillator arrays. SiPMs clearly have the potential to be the photodetector of choice for some, or even perhaps most, PET systems

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

This work presents a low-spur and low-jitter fractional-N digital phase-locked loop (PLL). To reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC), two novel solutions are introduced. First, the inverse-constant-slope DTC achieves high-linearity, thanks to its immunity to channel-length modulation and non-linear parasitic capacitances. Second, the frequency-control-word (FCW) sub-tractive dithering technique randomizes the quantization error of the ?S modulator driving the PLL divider ratio without requiring an increased DTC dynamic range and pushing the fractional spurs outside the PLL bandwidth. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.33 mm(2) and dissipates 17.2 mW. At fractional-N channels near 9.25 GHz, the measured in-band fractional spurs and the rms jitter are below -70 dBc and 77 fs, respectively, leading to a jitter-power figure of merit of -249.9 dB

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

This work presents a low-jitter and low out-of-band noise two-core fractional- $N$ digital bang-bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress the quantization noise (QN) of the digitally controlled oscillator (DCO) and to achieve an optimal trade between power consumption and PLL noise. The digital period averaging technique, working in background of the main system, enables the use of a low-power xor-based quadrupler for clocking $\Delta \Sigma$ modulator dithering the DCO tuning word. The true-in-phase combiner circuit implements a digitally assisted power combination of two PLL outputs, to optimally reduce the impact of the PLL noise sources. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.47 mm 2 and synthesizes frequencies from 8.5 to 10.5 GHz while dissipating 36 mW. The measured rms jitter (integrated from 1 kHz to 100 MHz and including spurs) is 72 fs for near-integer channels, with a worst case fractional spur of - 59.7 dBc, while the measured out-of-band noise is -140.7 dBc/Hz at a 10-MHz offset